This invention relates generally to electronic devices, and more specifically to a support substrate structure and method for forming an encapsulated electronic device.
Semiconductor chips typically are encapsulated within a device package prior to their installation into an electronic system. Leadless packaging is one type of chip packaging technology that has gained in popularity in recent years. Compared to other types of electronic packages, leadless packages have a smaller footprint and thinner profile. This makes leadless packages ideal for wireless, networking and other consumer electronic applications where tight space requirements are important.
Leadless packaging is typically based on traditional wire bonding and leadframe processes, which enables a very attractive cost structure compared to other small outline packages. By eliminating external leads, a package footprint is decreased by approximately one quarter to one half compared to similar leaded surface mount packages. Additionally, the die attach pad of a leadless package can be coupled directly to a next level of assembly such as a printed circuit board, which provides enhanced thermal performance.
There are several problems with current leadless packaging techniques that impact overall device performance. In a typical leadless packaging process flow, a semiconductor chip is attached to a metal leadframe using a solder die attach technique. When heated during the process, the die attach material spreads or flows out from beneath the chip across the leadframe. This can result in the chip tilting or rotating off of its desired location on the leadframe. When the chip tilts, regions of stress are localized in areas where the die attach material thickness is thin, which can lead to chip cracking. When a chip rotates off its desired location, alignment problems can occur during subsequent wire bond processing. Additionally, typical mold compounds or encapsulating materials do not adhere well to die attach materials, which can lead to package delamination, chip cracks, package cracks, or die attach cracks. This forces manufacturers to use smaller chips on a given leadframe to ensure sufficient bonding surface area for encapsulating material to adhere to, which is an inefficient use of space.
Accordingly, a need exists for low-cost methods and structures that reduce the spreading of die attach materials in electronic packaging processes and improve overall device performance and reliability.